/*
 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2021-2021. All rights reserved.
 * Description:  Interrupt DRIVER
 *
 * Create: 2021-10-13
 */
#include "stdint.h"
#include "chip_core_irq.h"
#include "los_hwi.h"

const uint8_t m_aucIntPri[BUTT_IRQN] = {
    LOSCFG_HWI_PRIO_LIMIT,   // USER_SOFTWARE_INT_IRQn            = 0,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_SOFTWARE_INT_IRQn      = 1,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT2_IRQn                = 2,
    OS_HWI_PRIO_LOWEST,      // MACHINE_SOFTWARE_INT_IRQn         = 3,
    LOSCFG_HWI_PRIO_LIMIT,   // USER_TIMER_INT_IRQn               = 4,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_TIMER_INT_IRQn         = 5,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT6_IRQn                = 6,
    LOSCFG_HWI_PRIO_LIMIT,   // MACHINE_TIMER_INT_IRQn            = 7,
    LOSCFG_HWI_PRIO_LIMIT,   // USER_EXTERNAL_INT_IRQn            = 8,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_EXTERNAL_INT_IRQn      = 9,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT10_IRQn               = 10,
    OS_HWI_PRIO_LOWEST,      // MACHINE_EXTERNAL_INT_IRQn         = 11,
    OS_HWI_PRIO_HIGHEST,     // NON_MASKABLE_INT_IRQn             = 12,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT13_IRQn               = 13,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT14_IRQn               = 14,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT15_IRQn               = 15,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT16_IRQn               = 16,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT17_IRQn               = 17,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT18_IRQn               = 18,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT19_IRQn               = 19,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT20_IRQn               = 20,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT21_IRQn               = 21,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT22_IRQn               = 22,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT23_IRQn               = 23,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT24_IRQn               = 23,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT25_IRQn               = 25,

    OS_HWI_PRIO_LOWEST,      // BT_INT0                           =  0,
    OS_HWI_PRIO_LOWEST,      // mcpu_acc_err_int                  =  1,
    OS_HWI_PRIO_LOWEST - 1,  // GADC_DONE                         =  2,
    OS_HWI_PRIO_LOWEST,      // GADC_ALARM                        =  3,
    OS_HWI_PRIO_LOWEST,      // HADC_DONE                         =  4,
    OS_HWI_PRIO_LOWEST,      // HADC_ALARM                        =  5,
    OS_HWI_PRIO_LOWEST,      // MCPU_PCLR_OK_INT                  =  6,
    OS_HWI_PRIO_LOWEST,      // ULP_GPIO                          =  7,
    OS_HWI_PRIO_LOWEST - 3,  // GPIO0                             =  8,
    OS_HWI_PRIO_LOWEST - 3,  // GPIO1                             =  9,
    OS_HWI_PRIO_HIGHEST,     // bt_toogle_pos_int                 = 10,
    OS_HWI_PRIO_HIGHEST,     // bt_toogle_neg_int                 = 11,
    OS_HWI_PRIO_LOWEST,      // KEY_SCAN_LOW_POWER                = 12,
    OS_HWI_PRIO_LOWEST,      // UART_L0                           = 13,
    OS_HWI_PRIO_LOWEST,      // MCU_CLDO_SYSLDO_VSET_INT          = 14,
    OS_HWI_PRIO_LOWEST - 2,  // UART_H0                           = 15,
    OS_HWI_PRIO_LOWEST,      // UART_L1                           = 16,
    OS_HWI_PRIO_LOWEST,      // SFC                               = 17,
    OS_HWI_PRIO_LOWEST,      // pdm_int                           = 18,
    OS_HWI_PRIO_LOWEST,      // SPI4_S                            = 19,
    OS_HWI_PRIO_LOWEST - 2,  // KEY_SCAN                          = 20,
    OS_HWI_PRIO_HIGHEST,     // M_WAKEUP                          = 21,
    OS_HWI_PRIO_HIGHEST,     // M_SLEEP                           = 22,
    OS_HWI_PRIO_LOWEST,      // M_RTC_0                           = 23,
    OS_HWI_PRIO_LOWEST,      // M_RTC_1                           = 24,
    OS_HWI_PRIO_LOWEST,      // M_RTC_2                           = 25,
    OS_HWI_PRIO_LOWEST,      // M_RTC_3                           = 26,
    OS_HWI_PRIO_LOWEST - 1,  // M_TIMER0                          = 27,
    OS_HWI_PRIO_LOWEST - 1,  // M_TIMER1                          = 28,
    OS_HWI_PRIO_LOWEST - 1,  // M_TIMER2                          = 29,
    OS_HWI_PRIO_LOWEST,      // M_TIMER3                          = 30,
    OS_HWI_PRIO_LOWEST,      // M_SDMA                            = 31,
    OS_HWI_PRIO_LOWEST,      // M_DMA                             = 32,
    OS_HWI_PRIO_LOWEST,      // SPI_MS0                           = 33,
    OS_HWI_PRIO_LOWEST,      // SPI_MS0                           = 34,
    OS_HWI_PRIO_LOWEST,      // SPI_MS0                           = 35,
    OS_HWI_PRIO_LOWEST,      // I2C0                              = 36,
    OS_HWI_PRIO_LOWEST,      // I2C1                              = 37,
    OS_HWI_PRIO_HIGHEST + 1,     // BT_BB_BT_IRQ                      = 38,
    OS_HWI_PRIO_HIGHEST + 1,     // BT_BB_BLE_IRQ                     = 39,
    OS_HWI_PRIO_HIGHEST + 1,     // BT_BB_GLE_IRQ                     = 40,
    OS_HWI_PRIO_LOWEST,      // I2S                               = 41,
    OS_HWI_PRIO_LOWEST,      // RF_PRT_INT                        = 42,
    OS_HWI_PRIO_HIGHEST + 2, // NFC_INT                           = 43,
    OS_HWI_PRIO_LOWEST,      // AFE_CMP_ALARM                     = 44,
    OS_HWI_PRIO_LOWEST,      // PWM0_INT                          = 45,
    OS_HWI_PRIO_LOWEST,      // PWM1_INT                          = 46,
    OS_HWI_PRIO_LOWEST,      // OSC_EN_WKUP                       = 47,
    OS_HWI_PRIO_LOWEST,      // OSC_EN_SLEEP                      = 48,
    OS_HWI_PRIO_LOWEST,      // M_TTCAN_INT0                      = 49,
    OS_HWI_PRIO_LOWEST,      // M_TTCAN_INT1                      = 50,
    OS_HWI_PRIO_LOWEST,      // MCU_BUCK_MICLDO_VSET_INT          = 51,
    OS_HWI_PRIO_HIGHEST,     // PMU_CMU_ERR                       = 52,
    OS_HWI_PRIO_LOWEST,      // ULP_INT                           = 53,
    OS_HWI_PRIO_LOWEST,      // AUX_ADC_INT                       = 54,
    OS_HWI_PRIO_LOWEST,      // S1_MONITOR_INT|S4_MONITOR_INT     = 55,
    OS_HWI_PRIO_LOWEST,      //                                   = 56,
    OS_HWI_PRIO_LOWEST,      // PULSE_CAPTURE_INT                 = 57,
    OS_HWI_PRIO_LOWEST,      // EH2H_BRG_INT                      = 58,
    OS_HWI_PRIO_LOWEST,      // clk_32k_det_done_sts              = 59,
    OS_HWI_PRIO_HIGHEST,     // ULP_WKUP_INT                      = 60,
    OS_HWI_PRIO_LOWEST,      // TSENSOR_INT_AON                   = 61,
    OS_HWI_PRIO_LOWEST - 3,  // QDEC_INT                          = 62,
    OS_HWI_PRIO_HIGHEST      // USB_INT                           = 63,
};
